Conventional processes for forming twin well regions in semiconductor wafers are generally costly. Separate masking and implant steps are typically used for the formation of each well type. In addition, using conventional processes, formation of a large surface step artifact at the well boundaries typically occurs, which artifact can result in a non-planar silicon substrate surface. FIGS. 3A through 3E illustrate a conventional method for forming a self-aligned twin well region. As illustrated in FIG. 3A, first, a silicon dioxide pad 301 is grown, and a silicon nitride layer 302 is then deposited. A photoresist mask 303 is then exposed, developed, and baked. The silicon nitride layer 302 is then etched, stopping at the silicon dioxide pad 301. As illustrated in FIG. 3B, next, the photoresist mask 303 is removed, and another photoresist mask 304 is exposed, developed, and baked. An ion implant of an n-type doping species is then performed on the unmasked portions of the silicon dioxide pad 301. As illustrated in FIG. 3C, the photoresist mask 304 is removed, and a layer of thermal oxide 305 is then grown, masked by the silicon nitride 302. As illustrated in FIG. 3D, the silicon nitride layer 302 is removed, and an ion implant of a p-type doping species is then performed. As illustrated in FIG. 3E, the silicon nitride layer 302 is then removed, and an oxide pad 306 is grown.
However, the twin-well region (comprising the NWELL and the PWELL) includes a permanent step height 307 at the well boundary, resulting in a non-planar surface. The non-planar surface can create major problems when shallow trench isolation is used on this surface. The difficulty is much greater when there is also a deep trench to be filled and planarized, as in the SMART-IS technologies, which use dual trench isolation. In addition to this, the active devices then lie at two separate optimum focus heights on the surface (the NMOS are in the PWELL, elevated above the surface of the NWELL which contains the PMOS devices). This complicates the lithography and makes the gate features difficult to pattern simultaneously.
Accordingly, there exists a need for a method for simplified processing for forming self-aligned twin well regions. The method should reduce the processing cost of forming twin well regions and substantially eliminate the large surface step artifact problem. The present invention addresses such a need.